2018.3:
 * Version 8.0 (Rev. 12)
 * No changes

2018.2:
 * Version 8.0 (Rev. 12)
 * No changes

2018.1:
 * Version 8.0 (Rev. 12)
 * No changes

2017.4:
 * Version 8.0 (Rev. 12)
 * No changes

2017.3:
 * Version 8.0 (Rev. 12)
 * General: Internal device family change, no functional changes

2017.2:
 * Version 8.0 (Rev. 11)
 * No changes

2017.1:
 * Version 8.0 (Rev. 11)
 * No changes

2016.4:
 * Version 8.0 (Rev. 11)
 * No changes

2016.3:
 * Version 8.0 (Rev. 11)
 * General: Enable support for future devices

2016.2:
 * Version 8.0 (Rev. 10)
 * No changes

2016.1:
 * Version 8.0 (Rev. 10)
 * Delivering only verilog simulation model, Stopped delivery of vhdl simulation model.

2015.4.2:
 * Version 8.0 (Rev. 9)
 * No changes

2015.4.1:
 * Version 8.0 (Rev. 9)
 * No changes

2015.4:
 * Version 8.0 (Rev. 9)
 * No changes

2015.3:
 * Version 8.0 (Rev. 9)
 * Delivering only vhdl simulation model, Stopped delivery of verilog simulation model.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:
 * Version 8.0 (Rev. 8)
 * No changes

2015.2:
 * Version 8.0 (Rev. 8)
 * No changes

2015.1:
 * Version 8.0 (Rev. 8)
 * Delivering unencrypted simulation files.
 * Supported devices and production status are now determined automatically, to simplify support for future devices

2014.4.1:
 * Version 8.0 (Rev. 7)
 * No changes

2014.4:
 * Version 8.0 (Rev. 7)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
 * Internal device family change, no functional changes

2014.3:
 * Version 8.0 (Rev. 6)
 * Reduced warnings in synthesis, no functional changes

2014.2:
 * Version 8.0 (Rev. 5)
 * Repackaged to improve internal automation, no functional changes.

2014.1:
 * Version 8.0 (Rev. 4)
 * Internal device family name change, no functional changes

2013.4:
 * Version 8.0 (Rev. 3)
 * Added support for Ultrascale devices

2013.3:
 * Version 8.0 (Rev. 2)
 * Enhanced support for IP Integrator
 * Reduced warnings in synthesis and simulation
 * Added support for Cadence IES and Synopsys VCS simulators

2013.2:
 * Version 8.0 (Rev. 1)
 * Repackaged to enable internal version management, no functional changes.

2013.1:
 * Version 8.0
 * Native Vivado Release
 * Unused port SPRA and its associated parameters removed.

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